1. general description the 74ahc2g32-q100; 74ahct2g32-q100 ar e high-speed si-gate cmos devices. they provide two 2-input or gates. the ahc device has cmos input switching leve ls and supply voltage range 2 v to 5.5 v. the ahct device has ttl input switching levels and supply voltage range 4.5 v to 5.5 v. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? symmetrical output impedance ? high noise immunity ? low power dissipation ? balanced propagation delays ? multiple package options ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) 3. ordering information 74ahc2g32-q100; 74ahct2g32-q100 dual 2-input or gate rev. 1 ? 12 march 2014 product data sheet table 1. ordering information type number package temperature range name description version 74AHC2G32DP-Q100 ? 40 ? c to +125 ? c tssop8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm sot505-2 74ahct2g32dp-q100 74ahc2g32dc-q100 ? 40 ? c to +125 ? c vssop8 plastic very thin sh rink small out line package; 8 leads; body width 2.3 mm sot765-1 74ahct2g32dc-q100
74ahc_ahct2g32_q100 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. al l rights reserved. product data sheet rev. 1 ? 12 march 2014 2 of 13 nxp semiconductors 74ahc2g32-q100; 74ahct2g32-q100 dual 2-input or gate 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. functional diagram 6. pinning information 6.1 pinning table 2. marking type number marking code [1] 74AHC2G32DP-Q100 a32 74ahct2g32dp-q100 c32 74ahc2g32dc-q100 a32 74ahct2g32dc-q100 c32 fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram (one gate) p q d $ % < $ % < p q d ? ? p q d % $ < fig 4. pin configuration sot505-2 (tssop8) and sot765-1 (vssop8) $ + & |